The present invention relates to spin transfer torque magnetic random access memory (STT-MRAM), and more particularly, to a method of manufacturing magnetic tunnel junction (MTJ) memory elements of STT-MRAM.
Spin transfer torque magnetic random access memory (STT-MRAM) is a new class of non-volatile memory, which can retain the stored information when powered off. An STT-MRAM device normally comprises an array of memory cells, each of which includes at least a magnetic memory element and a selection transistor coupled in series between appropriate electrodes. Upon application of an appropriate write current to the magnetic memory element, the electrical resistance of the magnetic memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
The magnetic memory element typically includes a magnetic reference layer and a magnetic free layer with an insulating tunnel barrier or junction layer interposed therebetween, thereby collectively forming a magnetic tunneling junction (MTJ). The magnetic reference layer has a fixed magnetization direction and may be anti-ferromagnetically exchange coupled to a magnetic pinned layer, which has a fixed but opposite or anti-parallel magnetization direction. Upon the application of an appropriate write current through the MTJ, the magnetization direction of the magnetic free layer can be switched between two directions: parallel and anti-parallel with respect to the magnetization direction of the magnetic reference layer. The insulating tunnel junction layer is normally made of a dielectric material with a thickness ranging from a few to a few tens of angstroms. When the magnetization directions of the magnetic free and reference layers are substantially parallel, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistivity of the MTJ. Conversely, the electrical resistivity of the MTJ is high when the magnetization directions of the magnetic reference and free layers are substantially anti-parallel. Accordingly, the stored logic in the magnetic memory element can be switched by changing the magnetization direction of the magnetic free layer.
Based on the relative orientation between the magnetic layers and the magnetization directions thereof, an MTJ can be classified into one of two types: in-plane MTJ, the magnetization directions of which lie substantially within planes parallel to the layer plane, or perpendicular MTJ, the magnetization directions of which are substantially perpendicular to the layer plane.
FIG. 1 illustrates the formation of an MTJ memory element 50 by a conventional plasma etching process. The MTJ memory element 50, which includes a patterned MTJ 52 formed between a bottom electrode 54 and a top electrode 56, is disposed on top of a bottom contact 58 embedded in a dielectric layer 60, which is formed on top of a substrate 62. The bottom electrode 54, the patterned MTJ 52, and the top electrode 56 of the MTJ memory element 50 are formed by etching a bottom electrode layer, a MTJ layer stack, and a top electrode layer with a etch mask thereon. The MTJ etching process is typically carried out with a reactive plasma etching process that utilizes a reactive gas chemistry, such as ethanol or carbon dioxide. However, the MTJ etching process etches the bottom electrode layer slowly and thus requires a thick hard mask, which would in turn require a thick photo mask and prevent shrinking of the device size. Using a different gas chemistry to accelerate the etching of the bottom electrode layer would likely damage the patterned MTJ 52 by forming a reaction layer thereon. Moreover, since the bottom contact 58, which is typically made of a conductive material such as copper, is exposed to the plasma towards the end of the MTJ etching process, metallic material sputtered from top of the bottom contact 58 may redeposit on the surface of the patterned MTJ 52, thereby causing electric shunting of the MTJ memory element 50.
For the foregoing reasons, there is a need for a fabrication method that is scalable with the device size and that does not damage the memory element.